Extraction of small signal equivalent circuit for de-embedding of 3D vertical nanowire transistor - Archive ouverte HAL Access content directly
Conference Papers Year : 2022

Extraction of small signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

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Abstract

In this paper, we present an improved methodology to extract the small signal electrical equivalent circuit of the parasitic elements using RF test-structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of parasitic elements from a virtual open structure constructed using electromagnatic simulation and calibrated against on-wafer S-parameter measurements up to 40 GHz. The electrical equivalent circuit of the passive device was then used for deembedding of the transistor S-parameters for extraction of intrinsic small signal parameters such as the gate capacitances.
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Dates and versions

hal-03864048 , version 1 (21-11-2022)

Identifiers

  • HAL Id : hal-03864048 , version 1

Cite

Bruno Neckel Wesling, Marina Deng, Mukherjee Chhandak, Abhishek Kumar, Guilhem Larrieu, et al.. Extraction of small signal equivalent circuit for de-embedding of 3D vertical nanowire transistor. 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2022), May 2022, Udine, Italy. à paraître. ⟨hal-03864048⟩
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