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Mapping Hard Real-Time Tasks on Network-on-Chip Manycore Architectures

Chawki Benchehida 1, 2 
2 SYCOMORES - Analyse symbolique et conception orientée composants pour des systèmes embarqués temps-réel modulaires
Inria Lille - Nord Europe, CRIStAL - Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189
Abstract : In this dissertation, we tackle the problem of execution complex multi-thread real-time applications on modern Network-on-Chip architectures. Network-on-Chip (NoC) is a promising technology that fits the increasing performance demands of Cyber-Physical Systems (CPS). The introduction of NoCs is justified by the fact that classical multi-core single-bus architectures fail to address the performance requirements and the predictability needs of modern CPS applications, especially as the number of cores increases. Even if the use of cache memories mitigates the bottleneck effect of single bus architectures, caches introduce unpredictable delays in accessing data, which in turn make it difficult to estimate the execution time of tasks. Most CPS applications are time-sensitive: tasks are assigned deadlines that must never exceed, otherwise a critical failure may occur. Such systems are denoted by hard real-time. Consequently, the communications that occur in the network, denoted by on-chip communications, must be predictable and as fast as possible to prevent deadline-missing. Since the task position on the NoC determines its communication cost, the allocation of the application tasks on the chip cores is a crucial problem. In this thesis, we address specifically the problem of allocating a set of real-time applications, each composed of several parallel tasks, whose structure is described by a Directed Acyclic Graph (DAG), onto a Network-on-Chip processor. First, we study the problem of bounding the communication cost depending on the different message scheduling policies at the router level. Then we address the problem of task scheduling and of verifying the schedulability of a certain allocation. Then, we propose an approach to reduce the complexity of the task allocation problem and its analysis cost. Moreover, we propose a task mapping strategy through a meta-heuristic which performs an effective design-space exploration for DAG (Directed Acyclic Graph) tasks. Lastly, in addition to on-chip communications, we studied the mapping problem when the off-chip communications are integrated into the model.
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Submitted on : Sunday, January 16, 2022 - 3:47:31 PM
Last modification on : Wednesday, September 7, 2022 - 8:14:05 AM


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  • HAL Id : tel-03514023, version 2


Chawki Benchehida. Mapping Hard Real-Time Tasks on Network-on-Chip Manycore Architectures. Embedded Systems. Université de Lille; Université d'Oran 1, 2021. English. ⟨tel-03514023v2⟩



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