Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures - Archive ouverte HAL Access content directly
Journal Articles International Journal of High Performance Systems Architecture (IJHPSA) Year : 2022

Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures

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Abstract

The Network-on-Chip (NoC) provides a viable solution to bus-contention problems in classical Multi/Many core architectures. However, NoC complex design requires particular attention to support the execution of real-time workloads. In fact, it is necessary to take into account task-to-core allocation and inter-task communication, so that all timing constraints are respected. The problem is more complex when considering task-to-main-memory communication, as the main memory is off-chip and usually connected to the network edges, within the 2D-Mesh topology, which generates a particular additional pattern of traffic. In this paper, we tackle these problems by considering the allocation of tasks and inter-task communications, and memory-to-task communications (modeled using Directed Acyclic Graphs DAGs) at the same time, rather than separating them, as it has been addressed in the literature of real-time systems. This problem is highly combinatorial, therefore our approach transforms it at each step, to a simpler problem until reaching the classical single-core scheduling problem. The goal is to find a trade-off between the problem combinatorial explosion and the loss of generality when simplifying the problem. We study the effectiveness of the proposed approaches using a large set of synthetic experiments.
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Dates and versions

hal-03595577 , version 1 (03-03-2022)

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Cite

Chawki Benchehida, Mohammed Kamel Benhaoua, Houssam Zahaf, Giuseppe Lipari. Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures. International Journal of High Performance Systems Architecture (IJHPSA), 2022, 11 (1), pp.1-11. ⟨10.1504/IJHPSA.2022.121877⟩. ⟨hal-03595577⟩
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