Fault Analysis Assisted by Simulation

Kais Chibani (1) , Adrien Facon (1) , Sylvain Guilley (2) , Damien Marion (1) , Yves Mathieu (2) , Laurent Sauvage (1) , Youssef Souissi (1) , Sofiane Takarabt (1)

1 Secure-IC S.A.S
2 LTCI - Laboratoire Traitement et Communication de l'Information

Side-channel and fault injection attacks are renown techniques to extract keys from cryptographic devices. Fortunately, leakage reduction and fault detection countermeasures exist and can be implemented right in the source-code. However, source-code level countermeasures might be altered during the compilation process. Design simulation is an effective means to detect such harmful simplifications. This is a well-known methodology to analyze regressions in terms of side-channel leakage. In this chapter, we explain that protections against fault injection attacks are no exception. First of all, we show that vulnerabilities to those attacks can be easily detected by simulation methods. Second, we highlight that simulation techniques are also highly efficient in detecting logic simplifications which destroy (fully or partly) the countermeasures. Thus, the simulation-based methodology we present in this chapter shows that it is possible to decide quickly which compilation options are safe and which ones are detrimental to the security.

Keywords: Fault injection attacks FIA; Hardware design simulation; Countermeasure analysis; Security verification; Hardware Description Language HDL

Domains: Computer Science [cs]; Cryptography and Security [cs.CR]

Kais Chibani, Adrien Facon, Sylvain Guilley, Damien Marion, Yves Mathieu, et al.. Fault Analysis Assisted by Simulation. Jakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩. ⟨hal-02915671⟩