Skip to Main content Skip to Navigation
Conference papers

Technology-agnostic power optimization for AES block cipher

Abstract : On the one hand, IoT applications require low-power consumption. On the other hand, they also need to embed strong cryptographic algorithms to protect the data they manipulate. We address this issue in the context of the AES block cipher. The challenge is to design an AES module consuming as little as possible, mostly by leveraging on the architecture. This paper presents two contributions. First of all, we present design guidelines for low-power AES, including lazy dataflow, glitch reduction techniques in combinational logic and algebraic simplification of diffusion operations. These optimizations allow to divide by two the power consumption of the AES module. Second , we show a methodology to improve the power consumption using a high-level technology-independent power and security evaluation tool (Virtualyzr).
Document type :
Conference papers
Complete list of metadata

Cited literature [12 references]  Display  Hide  Download
Contributor : Sylvain Guilley Connect in order to contact the contributor
Submitted on : Friday, August 14, 2020 - 7:47:16 PM
Last modification on : Wednesday, December 23, 2020 - 7:04:03 PM
Long-term archiving on: : Monday, November 30, 2020 - 8:02:13 PM


Files produced by the author(s)




Kais Chibani, Adrien Facon, Sylvain Guilley, Youssef Souissi. Technology-agnostic power optimization for AES block cipher. ICECS, Dec 2018, Bordeaux, France. pp.397-400, ⟨10.1109/ICECS.2018.8617921⟩. ⟨hal-02915635⟩



Record views


Files downloads