Compact Functional Testing for Neuromorphic Computing Circuits

Sarah A El-Sayed (1) , Theofilos Spyrou (1) , Luis A Camuñas-Mesa (2) , Haralampos-G. Stratigopoulos (1)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 IMSE-CNM - Instituto de Microelectrónica de Sevilla

We address the problem of testing Artificial Intelligence (AI) hardware accelerators implementing Spiking Neural Networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the inter-class spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassififed with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modelled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time.

Mots clés: Neuromorphic computing; spiking neural networks; testing; fault modeling; fault simulation

Domaines: Intelligence artificielle [cs.AI]; Ingénierie assistée par ordinateur; Micro et nanotechnologies/Microélectronique

Sarah A El-Sayed, Theofilos Spyrou, Luis A Camuñas-Mesa, Haralampos-G. Stratigopoulos. Compact Functional Testing for Neuromorphic Computing Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42 (7), pp.2391 - 2403. ⟨10.1109/TCAD.2022.3223843⟩. ⟨hal-03859719⟩