Guideline for test-structures placement for on-Wafer calibration in sub-THz Si device characterization

Chandan Yadav , Marco Cabbia (1) , Sebastien Fregonese (1) , Marina Deng (1) , Magali de Matos (1) , Thomas Zimmer (1)

1 IMS - Laboratoire de l'intégration, du matériau au système

In this paper, we present a guideline to optimize the layout floorplan by minimizing the impact of on-wafer neighbouring structures in very high frequency (1 GHz to 220 GHz) on-wafer measurements of Si electronic devices. To present the guideline, a 3D electromagnetic (EM) simulation is carried out extensively using a realistic EM model of a commercial RF probe. First layout design dependent factors influencing the DUT characteristics are identified which are 1) way of positioning of the on-wafer structures w.r.t. DUT (e.g. in line or checkerboard pattern) and 2) the spacing between on-wafer structures and the DUT. Afterwards, a guideline to reduce the influence of on-wafer neighbours on the DUT characteristics is presented. The optimization of the layout floorplan with minimal on-wafer neighbours prior to their fabrication also permits to reduce the costs with respect to occupied Si area.

Mots clés: On-wafer TRL calibration; test-structures; EM simulation; RF probes; Spatial placement; sub-THz

Domaines: Sciences de l'ingénieur [physics]

Chandan Yadav, Marco Cabbia, Sebastien Fregonese, Marina Deng, Magali de Matos, et al.. Guideline for test-structures placement for on-Wafer calibration in sub-THz Si device characterization. 2021 IEEE/MTT-S International Microwave Symposium - IMS 2021, Jun 2021, Atlanta, United States. pp.511-514, ⟨10.1109/IMS19712.2021.9574928⟩. ⟨hal-03851109⟩